PING Systems - intel 8085 microprocessor Simulator
Data Transfer
Arithmetic
Logical
Branching
Control
aci
Aci , Add immediate to accumulator with carry
Opcode Operand Bytes M-Cycles T-States Hex code
ACI 8-bit data 2 2 7 CE
Description:- The 8-bit data and carry flag are added to the
contents of the accumulator, and the result is stored in the
accumulator.
Flag:- All flags are modified to reflect the result of the addition.
Example:-
Initial state:- Regs/Mem Flags
A = 26H Cy=1
Instruction :- ACI 57H
Result :- Regs/Mem Flags
A = 7EH S=0, Z=0, Ac=0, P=1, Cy=0
Comments :-
1. After adition the previous carry flag is cleared.
2. This instruction is commonly used in 16-bit addition. This
instruction should not be used to account for a carry generated
by 8-bit numbers.
adc
Adc, Add register to accumulator with carry
Opcode Operand Bytes M-Cycles T-States Hex code
ADC Reg/ 1 1 4 Reg Hex
Mem 2 7 B 88
C 89
D 8A
E 8B
H 8C
L 8D
M 8E
A 8F
Description:- The contents of the operand (register or memory) and
and the Carry flag are added to the contents of the accumulator and
the result is placed in the accumulator. The contents of the operand
are not altered; however the previous carry flag is reset.
Flag:- All flags are modified to reflect the result of the addition.
Example:-
Initial state:- Regs/Mem Flags
A = 98H Cy=1
C = A1H
Instruction :- ADC C
Result :- Regs/Mem Flags
A = 3AH S=0, Z=0, Ac=0, P=1, Cy=0
Comments :-
1. After adition the previous carry flag is cleared.
2. This instruction is commonly used in 16-bit addition. This
instruction should not be used to account for a carry generated
by 8-bit numbers.
add
Add, Add register to accumulator
Opcode Operand Bytes M-Cycles T-States Hex code
ADD Reg/ 1 1 4 Reg Hex
Mem 2 7 B 80
C 81
D 82
E 83
H 84
L 85
M 86
A 87
Description:- The contents of the operand (register or memory) are
added to the contents of the accumulator and the result is placed in
the accumulator. If the operand is a memory location, that is
indicated by the 16-bit address in HL register.
Flag:- All flags are modified to reflect the result of the addition.
Example:-
Initial state:- Regs/Mem Flags
A = 47H
B = 51H
Instruction :- ADD B
Result :- Regs/Mem Flags
A = 98H S=1, Z=0, Ac=0, P=0, Cy=0
Example:-
Initial state:- Regs/Mem Flags
A = 76H
HL = 2050
[HL] = A2H
Instruction :- ADD B
Result :- Regs/Mem Flags
A = 18H S=0, Z=0, Ac=0, P=1, Cy=1
adi
Adi, Add immediate to accumulator
Opcode Operand Bytes M-Cycles T-States Hex code
ADI 8 bit data 2 2 7 C6
Description:- The 8-bit data(operand) are added to the contents of
the accumulator, and the result is placed in the accumulator.
Flag:- All flags are modified to reflect the result of the addition.
Example:-
Initial state:- Regs/Mem Flags
A = 4AH
Instruction :- ADI 59H
Result :- Regs/Mem Flags
A = A3H S=1, Z=0, Ac=1, P=1, Cy=0
ana
Ana, logical and with accumulator
Opcode Operand Bytes M-Cycles T-States Hex code
ANA Reg/ 1 1 4 Reg Hex
Mem 1 2 7 B A0
C A1
D A2
E A3
H A4
L A5
M A6
A A7
Description:- The contents of the accumulator are logically ANDed
with the contents of the operand(retister of memory), and the result
is placed in the accumulator. If the operand is a memory location,
its address is specified by the contents of HL register.
Flag:- S, Z, P are modified to reflect the result of the operation.
CY is reset and AC is set.
Example:-
Initial state:- Regs/Mem Flags
A = 54H
D = 82H
Instruction :- ANA D
Result :- Regs/Mem Flags
A = 00H S=0, Z=1, Ac=1, P=1, Cy=0
ani
Ani, and immediate with accumulator
Opcode Operand Bytes M-Cycles T-States Hex code
ANI 8 bit data 2 2 7 E6
Description:- The contents of the accumulator are logically ANDed
with the 8-bit data(operand) and the results are placed in the
accumulator.
Flag:- S, Z, P are modified to reflect the result of the operation.
CY is reset and AC is set.
Example:-
Initial state:- Regs/Mem Flags
A = A3H
Instruction :- ADI 97H
Result :- Regs/Mem Flags
A = 83H S=1, Z=0, Ac=1, P=0, Cy=0
call
Call, branch to a subroutine
Opcode Operand Bytes M-Cycles T-States Hex code
CALL 16-Bit Address 3 5 18 CD
Description:- The program sequence is transferred to the address
speficied by the operand. Before the transfer, the address of the
next instruction to CALL (the contents of the program counter) is
pushed on the stack. The sequence of events is described in the
example below.
Flag:- No flags are affected.
Example:- Write CALL instruction at memory location 2010H to call a
subroutine located at 2050H. Explain the sequence of events when the
stack pointer is at location 2099H.
Memory Address:- Hex code Mnemonics
2010 CD CALL 2050H
2011 50
2012 20
Note:- The address is stored in reverse byte sequence.
Execution of call:- The address in the program is placed on the stack
as follows.
1. Stack pointer is decremented.
2. MSB is stored.
3. Stack pointer is again decremented.
4. LSB is stored
5. Call address is temporarily stored in internal WZ registers and
placed on the bus for the fetch cycle.
Note:- A call to address 0005 will not invoke your subroutine even if
you have placed one, instead it will result in the execution of a
system call.
cc
cnc
cp
cm
cpe
cpo
cz
cnz
CC, CNC, CP, CM, CPE, CPO, CZ, CNZ Conditional calls
All the conditional calls have the format:-
conditional call 16-bit address
Opcode Description Flag Hex M-Cycles/T-States
CC Call on Carry CY=1 DC
CNC Call with no Carry CY=0 D4 (Applicable to all)
CP Call on positive S =0 F4 2M/9T if condition
CM Call on minus S =1 FC is not true
CPE Call on Parity Even P =1 EC 5M/17T if condition
CPO Call on Parity Odd P =0 E4 is true
CZ Call on Zero Z =1 CC
CNZ Call on No Zero Z =0 C4
Flag:- No flags are affected.
Note:- A call to address 0005 will not invoke your subroutine even if
you have placed one, instead it will result in the execution of a
system call.
cma
Cma, Complement accumulator
Opcode Operand Bytes M-Cycles T-States Hex code
CMA None 1 1 4 2f
Description:- The contents of the accumulator are complemented
Flag:- No flags are affected.
Example:-
Initial state:- Regs/Mem Flags
A = 89H
Instruction :- CMA
Result :- Regs/Mem Flags
A = 76H
cmc
Cmc, Complement carry
Opcode Operand Bytes M-Cycles T-States Hex code
CMC None 1 1 4 3F
Description:- The carry flag is complemented.
Flag:- The carry flag is modified, no other flags are affected.
cmp
Cmp, Compare with accumulator
Opcode Operand Bytes M-Cycles T-States Hex code
CMP Reg/ 1 1 4 Reg Hex
Mem 1 2 7 B B8
C B9
D BA
E BB
H BC
L BD
M BE
A BF
Description:- The contents of the operand(register or memory) are
compared with the contents of the accumulator. Both contents are
preserved and the compariosn is shown by setting the flags as follows
its address is specified by the contents of HL register.
if A<(reg/mem): Carry flag is set.
if A=(reg/mem): Zero flag is set.
if A>(reg/mem): Carry and Zero flags are reset.
The comparison of two bytes is performed by subtracting the contents
of the operand from the contents of the accumulator; however, neither
contents are modified.
Flag:- S, P, Ac are modified in addition to Z and C to reflect the
results of the operation.
Example:-
Initial state:- Regs/Mem Flags
A = 57H
B = 62H
Instruction :- CMP B
Result :- Regs/Mem Flags
S=1, Z=0, Ac=1, P=1, Cy=1
Note:- No register contents are changed
cpi
Cpi, Compare immediate with accumulator
Opcode Operand Bytes M-Cycles T-States Hex code
CPI 8-bit 2 2 7 FE
Description:- The second byte (8-bit data) is compared with the
accumulator. The value being compared remain unchanged and the
results of the comparison are indicated by setting the flags as
follows.
if A<(reg/mem): Carry flag is set.
if A=(reg/mem): Zero flag is set.
if A>(reg/mem): Carry and Zero flags are reset.
The comparison of two bytes is performed by subtracting the data byte
of the accumulator; however, neither contents are modified.
Flag:- S, P, Ac are modified in addition to Z and C to reflect the
results of the operation.
Example:-
Initial state:- Regs/Mem Flags
A = C2H
Instruction :- CPI 98H
Result :- Regs/Mem Flags
S=0, Z=0, Ac=0, P=0, Cy=0
þ The accumulator contents remain unchanged.
þ Z and CY flags are reset because [A] > Data
þ Other flags: S=0, AC=0, P=0
Example:-
Initial state:- Regs/Mem Flags
A = C2H
Instruction :- CPI C2H
Result :- Regs/Mem Flags
S=0, Z=1, Ac=0, P=1, Cy=0
þ The accumulator contents remain unchanged.
þ Z and CY flags are reset because [A] = Data
þ Other flags: S=0, AC=0, P=1
Note:- No register contents are changed
daa
Daa, Decimal adjust accumulator
Opcode Operand Bytes M-Cycles T-States Hex code
DAA none 1 1 4 27
Description:- The contents of the accumulator are changed from a
binary value to two 4-bit binary coded decimal(BCD) digits. This is
the only instruction that uses the auxiliary flag(internally) to
perform the binary to BCD conversion, and the conversion procedure is
described below.
Flag:- S, Z, Ac, P, CY flags are altered to reflect the results of
the operation. Instruction DAA converts the binary contents of
the accumulator as follows:
1. If the value of the low-order 4-bits(D3-D0) in the accumulator is
greater than 9 or if AC flag is set, the instruction adds 6 to the
low-order four bits.
2. If the value of the high-order 4-bits(D7-D4) in the accumulator is
greater than 9 or if the carry flag is set, the sintruction adds 6
to the high-order four bits.
Example:- Add decimal 68(BCD) to the accumulator, which contains
85(BCD)
A = 85(BCD) = 1 0 0 0 0 1 0 1
+ 68(BCD) = 0 1 1 0 1 0 0 0
============ ===================
153(BCD) = 1 1 1 0 1 1 0 1
The binary sum is EDH. The values of both, low-order and high-order
four bits are higher than 9. Add 6 to both.
= ED = 1 1 1 0 1 1 0 1
+ 66 = 0 1 1 0 0 1 1 0
1 1 1 1
============ ===================
153(BCD) = 1 0 1 0 1 0 0 0 1
. .
Cy Cy
The accumulator contains 53 and the carry flag is set to indicate
that the sum is larger than eight bits(153).
dad
Dad, Add register pair to H and L registers
Opcode Operand Bytes M-Cycles T-States Hex code
DAD reg-pair 1 3 10 Reg Hex
B 09
D 19
H 29
SP 39
Description:- The 16-bit contents of the specified register pair are
added to the contents of the HL register and the sum is saved in the
HL register and the sum is saved in the HL register. The contents of
the source register pair are not altered.
Flag:- If the result is larger than 16 bits the CY flag is set. No
other flags are affected.
Example:-
Initial state:- Regs/Mem Flags
HL = C2H
Instruction :- DAD HL
Result :- Regs/Mem Flags
HL = C2H Cy=0
Example:-
Initial state:- Regs/Mem Flags
HL = 05H
SP = 2099H
Instruction :- DAD SP
Result :- Regs/Mem Flags
HL = 209Eh Cy=0
þ After the execution of the instruction, the contents of the stack
pointer register are not altered.
dcr
Dcr, Decrement source by 1
Opcode Operand Bytes M-Cycles T-States Hex code
DCR REG/ 1 1 4 Reg Hex
MEM 1 3 10 B 05
C 0D
D 15
E 1D
H 25
L 2D
M 35
A 3D
Description:- The contents of the designated register/memory is
decremented by 1 and the results are stored in the same place. If
the operand is a memory location, it is specified by the contents of
the HL register pair.
Flag:- S, Z, P, AC are modified to reflect the result of the
operation. CY is not modified.
Example:-
Initial state:- Regs/Mem Flags
B = A0H
Instruction :- DCR B
Result :- Regs/Mem Flags
B = 9FH
dcx
Dcx, Decrement register pair by 1
Opcode Operand Bytes M-Cycles T-States Hex code
DCX reg-pair 1 1 6 Reg Hex
B 0B
D 1B
H 2B
SP 3B
Description:- The contents of the specified register pair are
decremented by 1. This instruction views the contents of the two
registers as a 16-bit number.
Flag:- No flags are affected.
Example:-
Initial state:- Regs/Mem Flags
DE= 0A234H
Instruction :- DCX B
Result :- Regs/Mem Flags
DE= 0A233H
di
Di, Disable interrupts
Opcode Operand Bytes M-Cycles T-States Hex code
DI None 1 1 4 F3
Description:- The Interrupt Enable flip-flop is reset and all the
interrupts except the TRAP are disabled.
Flag:- No flags are affected.
ei
Ei, Enable interrupts
Opcode Operand Bytes M-Cycles T-States Hex code
EI None 1 1 4 FB
Description:- The Interrupt Enable flip-flop is set and all the
interrupts except the TRAP are disabled.
Flag:- No flags are affected.
hlt
Hlt, Halt and enter wait state
Opcode Operand Bytes M-Cycles T-States Hex code
HLT None 1 2 or more 5 or more 76
Description:- The MPU finishes executing the current instruction and
halts any further execution.
Flag:- No flags are affected.
Note:- In the case of the emulator the 'hlt' instruction is used to
stop the execution of a program instead of the rst 1 instruction.
Also see :-
Proposed standard usage
in
In, Input data to accumulator from a port with 8-bit address
Opcode Operand Bytes M-Cycles T-States Hex code
IN 8-bit port 2 3 10 DB
Address
Description:- The contents of the input port designated in the
operand are read and loaded into the accumulator.
Flag:- No flags are affected.
inr
Inr, Increment contents of register/memory by 1
Opcode Operand Bytes M-Cycles T-States Hex code
INR Reg/ 1 1 4 Reg Hex
Mem 1 3 10 B 04
C 0C
D 14
E 1C
H 24
L 2C
M 34
A 3C
Description:- The contents of the designated register/memory are
incremented by 1 and the results are stored in the same place. If
the operand is a memory location, it is specified by the contents of
the HL register pair.
Flag:- S, Z, P, AC are modified to reflect the result of the
operation. CY is not modified.
Example:-
Initial state:- Regs/Mem Flags
D = FFH
Instruction :- INR D
Result :- Regs/Mem Flags
D = 00H
Note:- Register D contains 00H, however no carry flag is set
inx
Inx, Increment register pair by 1
Opcode Operand Bytes M-Cycles T-States Hex code
INX reg-pair 1 1 6 Reg Hex
B 03
D 13
H 23
SP 33
Description:- The contents of the specified register pair are
incremented by 1. The instruction views the contents of the two
registers as a 16-bit number.
Flag:- No flags are affected.
Example:-
Initial state:- Regs/Mem Flags
HL= 9FFFH
Instruction :- INX H
Result :- Regs/Mem Flags
HL= A000H
jmp
Jump unconditionally
Opcode Operand Bytes M-Cycles T-States Hex code
JMP 16-Bit Address 3 5 18 C3
Description:- The program sequence is transferred to the address
speficied by the 16-bit address. This is a 3-byte instruction, the
second byte specifies the low-order byte and third byte specifies the
high-order byte.
Flag:- No flags are affected.
Example:- Write a JMP instruction at memory location 2000H to
transfer the program sequence to memory location 2050H.
Memory Address:- Hex code Mnemonics
2000 C3 JMP 2050H
2001 50
2002 20
Note:- The address is stored in reverse byte sequence.
jc
jnc
jp
jm
jpe
jpo
jz
jnz
JC, JNC, JP, JM, JPE, JPO, JZ, JNZ Jump Conditionally
All the conditional jumps have the format:-
conditional jump 16-bit address
Opcode Description Flag Hex M-Cycles/T-States
JC Jump on Carry CY=1 DA
JNC Jump with no Carry CY=0 D2 (Applicable to all)
JP Jump on positive S =0 F2 2M/7T if condition
JM Jump on minus S =1 FA is not true
JPE Jump on Parity Even P =1 EA 3M/10T if condition
JPO Jump on Parity Odd P =0 E2 is true
JZ Jump on Zero Z =1 CA
JNZ Jump on No Zero Z =0 C2
Flag:- No flags are affected.
lda
Lda, Load accumulator direct
Opcode Operand Bytes M-Cycles T-States Hex code
LDA 16-bit Address 3 4 13 3A
Description:- The contents of a memory location, specified by a
16-bit address in the operand, are copied to the accumulator. The
contents of the source are not altered. This is a 3-byte instruction,
the second byte specifies the low-order address and the third byte
specifies the high-order address.
Flag:- No flags are affected.
Example:-
Initial state:- Regs/Mem Flags
[2050H] = F8H
Instruction :- LDA 2050H
Result :- Regs/Mem Flags
A = F8H
ldax
Ldax, Load accumulator indirect
Opcode Operand Bytes M-Cycles T-States Hex code
LDAX B/D register 1 2 7 Reg Hex
BC 0A
DE 1A
Description:- The contents of the designated register pair to a
memory location. This instruction copies the contents of that memory
into the accumulator. The contents of either the register pair or
the memory location are not altered.
Flag:- No flags are affected.
Example:-
Initial state:- Regs/Mem Flags
[2050H] = 9FH
BC = 2050H
Instruction :- LDAX B
Result :- Regs/Mem Flags
A = 9FH
lhld
Lhld, Load H and L registers direct
Opcode Operand Bytes M-Cycles T-States Hex code
LHLD 16-bit address 3 5 16 2A
Description:- The instruction copies the contents of the memory
location pointed out by the 16-bit address in register L and copies
the contents of the next memory location in register H. The contents
of source memory locations are not altered.
Flag:- No flags are affected.
Example:-
Initial state:- Regs/Mem Flags
[2050H] = 9FH
BC = 2050H
Instruction :- LDAX B
Result :- Regs/Mem Flags
A = 9FH
lxi
Lxi, Load register pair immediate
Opcode Operand Bytes M-Cycles T-States Hex code
LXI 16-bit address 3 5 10 Reg Hex
B 01
D 11
H 21
SP 31
Description:- The instruction loads 16-bit data in the register pair
designated in the operand. This is a 3-byte instruction, the second
byte specifies the low-order byte and the thirde byte specifies the
the high-order byte.
Flag:- No flags are affected.
Example:-
Initial state:- Regs/Mem Flags
Instruction :- LXI B,2050H
Result :- Regs/Mem Flags
BC = 2050H
Note:- The data '2050h' is entered in reverse byte sequence.
mov
Move, Copy from source to destination
Opcode Operand Bytes M-Cycles T-States Hex code
MOV Rd,Rs 1 1 4
MOV Mem,Rs 1 2 7
MOV Rd,Mem 1 2 7
Description:- This instruction copies the contents of the source
into the destination register, the contents of the source register
are not altered. If one of the operands is a memory location, it is
specified by the contetns of HL registers.
Flag:- No flags are affected.
Source location
B C D E H L M A
=================================
B | 40 41 42 43 44 45 46 47
C | 48 49 4A 4B 4C 4D 4E 4F
Destination D | 50 51 52 53 54 55 56 57
E | 58 59 5A 5B 5C 5D 5E 5F
Location H | 60 61 62 63 64 65 66 67
L | 68 69 6A 6B 6C 6D 6E 6F
M | 70 71 72 73 74 75 -- 77
A | 78 79 7A 7B 7C 7D 7E 4F
Example:-
Initial state:- Regs/Mem Flags
B = 34H
Instruction :- MOV A,B
Result :- Regs/Mem Flags
A = 34H
Example:-
Initial state:- Regs/Mem Flags
HL = 2050H
[2050] = 9FH
Instruction :- MOV B,M
Result :- Regs/Mem Flags
B = 9FH
mvi
Mvi, Move immediate 8-bit
Opcode Operand Bytes M-Cycles T-States Hex code
MVI Reg, Data 2 2 7 Reg Hex
Mem, Data 2 3 10 B 06
C 0E
D 16
E 1E
H 26
L 2E
M 36
A 3E
Description:- The 8-bit data is stored in the destination register
or memory. If the operand is a memory location, it is specified by
the contents of HL registers.
Flag:- No flags are affected.
Example:-
Initial state:- Regs/Mem Flags
Instruction :- MVI B,92H
Result :- Regs/Mem Flags
B = 92H
nop
Nop, No operation
Opcode Operand Bytes M-Cycles T-States Hex code
NOP None 1 1 4 00
Description:- No operation is performed. The instruction is fetched
and decoded; however, no operation is executed.
Flag:- No flags are affected.
Comments:- The instruction is used to fill in time delays or to
delete and insert instructions while troubleshooting.
ora
Ora, Logically or with accumulator
Opcode Operand Bytes M-Cycles T-States Hex code
ORA Reg 1 1 4 Reg Hex
Mem 1 2 7 B B0
C B1
D B2
E B3
H B4
L B5
M B6
A B7
Description:- The contents of the accumulator are logically Ored
with the contents of the operand(register or memory), and the results
are placed in the accumulator. If the operand is a memory location,
its address is specified by the contents of HL registers.
Flag:- Z, S, P are modified to reflect the results of the operation.
AC and CY are reset.
Example:-
Initial state:- Regs/Mem Flags
A = 03H
B = 81H
Instruction :- ORA C
Result :- Regs/Mem Flags
A = 83H S=1, Z=0, Ac=0, P=0, Cy=0
03H = 0 0 0 0 0 0 1 1
81H = 1 0 0 0 0 0 0 1
============ ===================
83H = 1 0 0 0 0 0 1 1
Comments:- This instruction is commonly used to
þ Reset the CY flag by ORing the contents of the accumulator with
itself
þ Set the Zero flag when 0 is loaded into the accumulator by ORing
the contents of accumulator with itself.
þ Combine bits from different registers.
ori
Ori, Logically OR immediate
Opcode Operand Bytes M-Cycles T-States Hex code
ORI 8-bit data 2 2 7 F6
Description:- The contents of the accumulator are logically ORed with
the 8-bit data in the operand and the results are placed in the
accumulator.
Flag:- S, Z, P are modified to reflect the results of the operation.
CY and AC are reset.
out
Out, Output data from accumulator to a port with 8-bit address
Opcode Operand Bytes M-Cycles T-States Hex code
OUT 8-bit port 2 3 10 D3
Address
Description:- The contents of the accumulator are copied into the I/O
port specified by the operand.
Flag:- No flags are affected.
pchl
Pchl, Load program counter with HL contents
Opcode Operand Bytes M-Cycles T-States Hex code
PCHL None 1 1 6 E9
Description:- The contents of register H and L are copied into the
program counter. The contents of H are placed as a high-order byte
and of L as a low-order byte.
Flag:- No flags are affected.
Comments:- This instruction is equivalent to a 1-byte unconditional
jump instruction. A program sequence can be changed to any location
by usimply loading the H and L registers with the appropriate address
and by using this instruction.
pop
Pop, Pop off stack to register pair
Opcode Operand Bytes M-Cycles T-States Hex code
POP Reg-pair 1 3 10 Reg Hex
B C1
D D1
H E1
PSW F1
Description:- The contents of the memory location pointed out by the
stack pointer register are copied to the low-order register(such as
(C,E,L, and flags) of the operand. The stack pointer is incremented
by 1 and the contents of that memory location are copied to the high
order register (B,D,H,A) of the operand. The stack pointer register
is again incremented by 1.
Flag:- No flags are modified.
Example:-
Initial state:- Regs/Mem Flags
SP = 2090H
[2090] = F5H
[2091] = 01H
Instruction :- POP H
Result :- Regs/Mem Flags
SP = 2092H
HL= 01F5H
Comments:- Operand PSW (Program Status Word) represents the contents
of the accumulator and the flag, the accumulator is the high-order
register and the flags are the low-order register.
þ The contents of the source, stack locations,are not altered after
the POP instruction.
push
Push, Push register pair onto stack+
Opcode Operand Bytes M-Cycles T-States Hex code
PUSH Reg-pair 1 3 10 Reg Hex
B C5
D D5
H E5
PSW F5
Description:- The contents of the register pair designated in the
operand are copied into the stack in the following sequence. The
stack pointer register is decremented and the contents of the high-
order register(B, D, H, A) are copied into that location. The stack
pointer register is decremented again and the contents of the
low-order register (C, E, L, flags) are copied to that location.
Flag:- No flags are modified.
Example:-
Initial state:- Regs/Mem Flags
SP = 2099H
BC = 3257H
Instruction :- PUSH B
Result :- Regs/Mem Flags
SP = 2097
[2097] = 57H
[2098] = 32H
Comments:- Operand PSW (Program Status Word) represents the contents
of the accumulator and the flag, the accumulator is the high-order
register and the flags are the low-order register.
þ The contents of the source registers are not altered after the
PUSH instruction.
ral
Ral, Rotate accumulator left through carry
Opcode Operand Bytes M-Cycles T-States Hex code
RAL None 1 1 4 17
Description:- Each binary bit of the accumulator is rotated left by
one position through the Carry flag. Bit D7 is placed in the bit in
the Carry flag and the Carry flag is placed in the least significant
position D0.
Flag:- CY is modified according to bit D7.
S, Z, AC, P are not affected.
Example:-
Initial state:- Regs/Mem Flags
A = A7H CY=0
Instruction :- RAL
Result :- Regs/Mem Flags
A = 4EH CY=1
Accumulator contents before instruction
CY = 0
accumulator = 1 0 1 0 0 1 1 1
Accumulator contents after instruction
CY = 1
accumulator = 0 1 0 0 1 1 1 0
Comments:- This instruction effectively provides a 9 bit
accumulator. The original contents of the accumulator can be
restored by using instruction RAR (Rotate Accumulator Right through
Carry). However, the contents will be modified if the instruction
rrc (Rotate Accumulator Right) is used to restore the contents.
rar
Rar, Rotate accumulator right through carry
Opcode Operand Bytes M-Cycles T-States Hex code
RAR None 1 1 4 1F
Description:- Each binary bit of the accumulator is rotated right
by one position through the Carry flag. Bit D0 is placed in the bit
in the Carry flag and the Carry flag is placed in the most
significant position D7.
Flag:- CY is modified according to bit D0.
S, Z, AC, P are not affected.
Example:-
Initial state:- Regs/Mem Flags
A = A7H CY=0
Instruction :- RAR
Result :- Regs/Mem Flags
A = 53H CY=1
Accumulator contents before instruction
CY = 0
accumulator = 1 0 1 0 0 1 1 1
Accumulator contents after instruction
CY = 1
accumulator = 0 1 0 1 0 0 1 1
rlc
Rlc, Rotate accumulator left
Opcode Operand Bytes M-Cycles T-States Hex code
RLC None 1 1 4 07
Description:- Each binary bit of the accumulator is rotated left by
one position. Bit D7 is placed in the position of D0 as well as in
the Carry flag.
Flag:- CY is modified according to bit D7.
S, Z, AC, P are not affected.
Example:-
Initial state:- Regs/Mem Flags
A = A7H CY=0
Instruction :- RAL
Result :- Regs/Mem Flags
A = 4FH CY=1
Accumulator contents before instruction
CY = 0
accumulator = 1 0 1 0 0 1 1 1
Accumulator contents after instruction
CY = 1
accumulator = 0 1 0 0 1 1 1 1
Comments:- The contents of bit D7 are placed in bit D0, and the
carry flag is modified accordingly. However, the contents of the
crry are not placed in bit D0 as in instruction ral.
rlc
Rrc, Rotate accumulator right
Opcode Operand Bytes M-Cycles T-States Hex code
RRC None 1 1 4 0F
Description:- Each binary bit of the accumulator is rotated right
by one position. Bit D0 is placed in the position of D7 as well as
in the Carry flag.
Flag:- CY is modified according to bit D0.
S, Z, AC, P are not affected.
Example:-
Initial state:- Regs/Mem Flags
A = A7H CY=0
Instruction :- RAL
Result :- Regs/Mem Flags
A = D3H CY=1
Accumulator contents before instruction
CY = 0
accumulator = 1 0 1 0 0 1 1 1
Accumulator contents after instruction
CY = 1
accumulator = 1 1 0 1 0 0 1 1
Comments:- The contents of bit D0 are placed in bit D7, and the
carry flag is modified accordingly. However, the contents of the
crry are not placed in bit D7 as in instruction rar.
ret
Ret, Return from subroutine unconditionally
Opcode Operand Bytes M-Cycles T-States Hex code
RLC None 1 3 10 C9
Description:- The program sequence is transferred from the
subroutine to the calling program. The two bytes from the top of
the stack are copied into the program counter and the program
execution begins at the new address. The instruction is equivalent
to pop program counter.
Flag:- No flags are affected.
Example:-
Initial state:- Regs/Mem Flags
SP = 2095H
[2095] = 50
[2096] = 20
Instruction :- RET
Result :- Regs/Mem Flags
SP = 2097H
IP = 2050H
Comments:- This instruction is used in conjunction with call or
conditional call instructions.
rc
rnc
rp
rm
rpe
rpo
rz
rnz
RC, RNC, RP, RM, RPE, RPO, RZ, RNZ Return Conditionally
All the conditional returns have the format:-
conditional return 16-bit address
Opcode Description Flag Hex M-Cycles/T-States
RC Return on Carry CY=1 D8
RNC Return with no Carry CY=0 D0 (Applicable to all)
RP Return on positive S =0 F0 1M/6T if condition
RM Return on minus S =1 F8 is not true
RPE Return on Parity Even P =1 E8 3M/12T if condition
RPO Return on Parity Odd P =0 E0 is true
RZ Return on Zero Z =1 C8
RNZ Return on No Zero Z =0 C0
Flag:- No flags are affected.
rim
RIM, Read Interrupt Mask
Opcode Operand Bytes M-Cycles T-States Hex code
RIM None 1 1 4 20
Description:- This is a multipurpose instruction used to read the
status of interrupts 7.5, 6.5, 5.5 and read serial data input bit.
The instruction loads eight bits in the accumulator with the
following interpretations:
D7 D6 D5 D4 D3 D2 D1 D0
====Ë===Ë===Ë===Ë===Ë===Ë===Ë===Â
|SIDÊ i7Ê i6Ê i5Ê IEÊ7.5Ê6.5Ê5.5
ÅÆÆÆÌÆÆÆÌÆÆÆÌÆÆÆÌÆÆÆÌÆÆÆÌÆÆÆÌÆÆÆÇ
Serial Input ÆÆÇ ÅÆÆÆÌÆÆÆÇ | ÅÆÆÆÌÆÆÆÇ
data bit | ÅÆÆ Interrupt masked
| if bit = 1
|
Interrupt pending ÆÆÇ ÅÆÆ Interrupt enable
if bit = 1 flip-flop is set
if bit = 1
Flag:- No flags are affected.
Example:-
Initial state:- Regs/Mem Flags
Instruction :- RIM
Result :- Regs/Mem Flags
A = Hex value as explained above
Also see :-
Rim/Sim details
rst
RST Restart Instruction
Opcode Binary Code Hex Restart Address
RST 0 1 1 0 0 0 1 1 1 C7 0000
RST 1 1 1 0 0 1 1 1 1 CF 0008
RST 2 1 1 0 1 0 1 1 1 D7 0010
RST 3 1 1 0 1 1 1 1 1 DF 0018
RST 4 1 1 1 0 0 1 1 1 E7 0020
RST 5 1 1 1 0 1 1 1 1 EF 0028
RST 6 1 1 1 1 0 1 1 1 F7 0030
RST 7 1 1 1 1 1 1 1 1 FF 0038
Description:- The RST instructions are equivalent to 1-byte call
instructions to one of the eight memory locations on page 0. The
instructions are generally used in conjunction with interrupts and
inserted using external hardware. However, these can be used as
software instructions in a program to transfer program execution to
one of the eight locations.
Flag:- No flags are affected.
sbb
Sbb, Subtract source and Borrow from accumulator
Opcode Operand Bytes M-Cycles T-States Hex code
SBB Reg/ 1 1 4 Reg Hex
Mem 2 7 B 98
C 99
D 9A
E 9B
H 9C
L 9D
M 9E
A 9F
Description:- The contents of the operand (register or memory) and
and the Borrow flag are subtracted from the contents of the
accumulator and the results are placed in the accumulator. The
contents of the operand are not altered; however the previous borrow
flag is reset.
Flag:- All flags are modified to reflect the result of the addition.
Example:-
Initial state:- Regs/Mem Flags
A = 37H Cy=1
B = 3FH
Instruction :- SBB B
Result :- Regs/Mem Flags
A = F7H S=1, Z=0, Ac=0, P=0, Cy=1
The borrow flag is set to indicate the result is in 2's complement.
The previous Borrow flag is reset during the subtraction.
sbi
Sbi , Subtract immediate with borrow
Opcode Operand Bytes M-Cycles T-States Hex code
SBI 8-bit data 2 2 7 DE
Description:- The 8-bit data and borrow flag are subtracted from the
contents of the accumulator, and the result is stored in the
accumulator.
Flag:- All flags are modified to reflect the result of the operation
Example:-
Initial state:- Regs/Mem Flags
A = 37H Cy=1
Instruction :- SBI 25H
Result :- Regs/Mem Flags
A = 11H S=0, Z=0, Ac=1, P=1, Cy=0
Comments :-
1. After adition the previous carry flag is cleared.
2. This instruction is commonly used in 16-bit addition. This
instruction should not be used to account for a carry generated
by 8-bit numbers.
shld
Shld, Store H and L registers direct
Opcode Operand Bytes M-Cycles T-States Hex code
SHLD 16-bit Address 3 5 16 22
Description:- The contents of register L are stored in the memory
location specified by the 16-bit address in the operand and the
contents of H register are stored in the next memory location by
location by incrementing the operand. The contents of registers HL
are not altered. This is a 3-byte instruction, the second byte
specifies low-order address and the third byte specifies the high
order address.
Flag:- No flags are affected.
Example:-
Initial state:- Regs/Mem Flags
HL = 01FFH
Instruction :- SHLD 2050H
Result :- Regs/Mem Flags
A = A3H
sim
SIM, Set interrupt Mask
Opcode Operand Bytes M-Cycles T-States Hex code
SIM None 1 1 4 30
Description:- This is a multipurpose instruction used to implement
the 8085 interrupts (RST 7.5, 6.5, 5.5) and serial data output.
The instruction interprets the accumulator contents as follows:
following interpretations:
D7 D6 D5 D4 D3 D2 D1 D0
====Ë===Ë===Ë===Ë===Ë===Ë===Ë===Â
|SODÊSDEÊXXXÊR75ÊMSEÊ7.5Ê6.5Ê5.5
ÅÆÆÆÌÆÆÆÌÆÆÆÌÆÆÆÌÆÆÆÌÆÆÆÌÆÆÆÌÆÆÆÇ
Serial OutputÆÆÇ | ÅÆÆÆÌÆÆÆÇ
data bit | ÅÆÆ Interrupt masked
| if bit = 1
|
Serial data ÆÆÆÆÆÆÇ ÅÆÆ Mask set enable
enable if bit = 1
1 = Enable
0 = Disable Reset R7.5 if = 1
Flag:- No flags are affected.
þ R75 - Reset RST 7.5 : If this bit=1, RST 7.5 flip-flop is reset
This is an additional control to reset RST 7.5
þ MSE - Mase set enable : If this bit is high, it enables the
functions of bits D2, D1, D0. This is a master control over all
the interrupt masking bits. If this bit is low, bits D2,D1 and
D0 do not have any effect on the masks
þ 7.5 = 0, RST 7.5 is enabled.
= 1, RST 7.5 is masked or disabled.
þ 6.5 = 0, RST 6.5 is enabled.
= 1, RST 6.5 is masked or disabled.
þ 5.5 = 0, RST 5.5 is enabled.
= 1, RST 5.5 is masked or disabled.
Example:-
Initial state:- Regs/Mem Flags
Instruction :- SIM
Result :- Regs/Mem Flags
A = Hex value as explained above
Also see :-
Rim/Sim details
sphl
Sphl, Copy H and L registers to the stack pointer
Opcode Operand Bytes M-Cycles T-States Hex code
SPHL None 1 1 6 F9
Description:- The instruction loads the contents of H and L
registers into the stack pointer register, the contents of the H
register provide the high-order address and the contents of the L
register provide the low-order address. The contents of the H and L
registers are not altered.
Flag:- No flags are affected.
sta
STA, Store accumulator direct
Opcode Operand Bytes M-Cycles T-States Hex code
LDA 16-bit Address 3 4 13 32
Description:- The contents of the accumulator are copied to a memory
location specified by the operand. This is a 3-byte instruction, the
second byte specifies the low-order address and the third byte
specifies the high-order address.
Flag:- No flags are affected.
Example:-
Initial state:- Regs/Mem Flags
A = 9FH
Instruction :- STA 2050H
Result :- Regs/Mem Flags
[2050H] = 9FH
stax
Stax, Store accumulator indirect
Opcode Operand Bytes M-Cycles T-States Hex code
STAX B/D register 1 2 7 Reg Hex
BC 02
DE 12
Description:- The contents of the accumulator are copied into the
accumulator are copied into the memory location specified by the
contents of the operand (register pair). The contents of the
accumulator contents in memory location 2050H.
Flag:- No flags are affected.
Example:-
Initial state:- Regs/Mem Flags
A = F9H
BC = 2050H
Instruction :- STAX B
Result :- Regs/Mem Flags
[2050] = F9H
stc
STC, Set carry
Opcode Operand Bytes M-Cycles T-States Hex code
STC None 1 1 4 37
Description:- The carry flag is set to 1.
Flag:- No other flags are affected.
sub
Sub, Subtract register or memory from accumulator
Opcode Operand Bytes M-Cycles T-States Hex code
SUB Reg/ 1 1 4 Reg Hex
Mem 2 7 B 90
C 91
D 92
E 93
H 94
L 95
M 96
A 97
Description:- The contents of the register or the memory location
specified by the operand are subtracted from the contents of the
accumulator, and the results are placed in the accumulator. The
contents of the source are not altered.
Flag:- All flags are modified to reflect the result of the operation
Example:-
Initial state:- Regs/Mem Flags
A = 37H
C = 40H
Instruction :- SUB C
Result :- Regs/Mem Flags
A = F7H S=1, Z=0, Ac=0, P=0, Cy=1
sui
Sui, Subtract immediate from accumulator
Opcode Operand Bytes M-Cycles T-States Hex code
SUI 8 bit data 2 2 7 D6
Description:- The 8-bit data (the operand) is subtracted from the
contents of the accumulator and the results are placed in the
accumulator.
Flag:- All flags are modified to reflect the result of the addition.
Example:-
Initial state:- Regs/Mem Flags
A = 40H
Instruction :- SUI 37H
Result :- Regs/Mem Flags
A = 9H S=0, Z=0, Ac=0, P=1, Cy=0
xchg
XCHG, Exchange H and L with D and E
Opcode Operand Bytes M-Cycles T-States Hex code
XCHG None 1 1 4 EB
Description:- The contents of register H are exchanged with the
contents of register D, and the contents of register L are exchanged
with the contents of register E.
Flag:- No flags are affected.
xra
Xra, Exclusive or with accumulator
Opcode Operand Bytes M-Cycles T-States Hex code
XRA Reg/ 1 1 4 Reg Hex
Mem 1 2 7 B A8
C A9
D AA
E AB
H AC
L AD
M AE
A AF
Description:- The contents of the operand(register or memory) are
Exclusive ORed with the contents of the accumulator, and the results
are placed in the accumulator. The contents of the operand are not
modified.
Flag:- Z, S, P are modified to reflect the results of the operation.
AC and CY are reset.
Example:-
Initial state:- Regs/Mem Flags
A = 77H
D = 56H
Instruction :- XRA D
Result :- Regs/Mem Flags
A = 21H S=0, Z=0, Ac=0, P=1, Cy=0
03H = 0 0 0 0 0 0 1 1
81H = 1 0 0 0 0 0 0 1
============ ===================
83H = 1 0 0 0 0 0 1 1
xri
Xri, Exclusive OR immediate with accumulator
Opcode Operand Bytes M-Cycles T-States Hex code
XRI 8-bit data 2 2 7 EE
Description:- The 8-bit data (operand) is Exclusive ORed with the
contents of the accumulator and the results are place in the
accumulator.
Flag:- S, Z, P are modified to reflect the results of the operation.
CY and AC are reset.
Example:-
Initial state:- Regs/Mem Flags
A = 8FH
Instruction :- XRI A2H
Result :- Regs/Mem Flags
A = 2DH S=0, Z=0, Ac=0, P=1, Cy=0
8FH = 1 0 0 0 1 1 1 1
A2H = 1 0 1 0 0 0 1 0
============ ===================
2DH = 0 0 1 0 1 1 0 1
xthl
Xthl, Exchange H and L with Top of stack
Opcode Operand Bytes M-Cycles T-States Hex code
XTHL None 2 2 7 EE
Description:- The contents of the L register are exchanged with the
stack location pointed out by the contents of the stack pointer
register. The contents of the H register are exchanged with the next
stack location (SP+1); however, the contents of the stack pointer
register are not altered.
Flag:- No flags are affected.
Example:-
Initial state:- Regs/Mem Flags
HL = A257H
[2095] = 38H
[2096] = 67H
Instruction :- XTHL
Result :- Regs/Mem Flags
HL = 6738H
[2095] = 57H
[2096] = A2H
Hexadecimal order
Instruction summary by Hexadecimal Order
Hex Mnemonic Group Hex Mnemonic Group
====================================================================
00 nop Control | 00 nop Control
01 lxi B Data transfer | 01 lxi Data transfer
02 stax B Data transfer | 01 lxi Data transfer
03 inx B Control | 00 nop Control
04 inr B Data transfer | 01 lxi Data transfer
05 dcr B Data transfer | 01 lxi Data transfer
06 mvi B Control | 00 nop Control
07 rlc Data transfer | 01 lxi Data transfer
09 dad B Data transfer | 01 lxi Data transfer
0A ldax B Control | 00 nop Control
0B dcx B Data transfer | 01 lxi Data transfer
0C inr C Data transfer | 01 lxi Data transfer
0D dcr C Data transfer | 01 lxi Data transfer
0E mvi C Control | 00 nop Control
0F rrc Data transfer | 01 lxi Data transfer
11 lxi D Data transfer | 01 lxi Data transfer
12 stax D Control | 00 nop Control
13 inx D Control | 00 nop Control
14 inr D Data transfer | 01 lxi Data transfer
15 dcr D Data transfer | 01 lxi Data transfer
16 mvi D Control | 00 nop Control
17 ral Data transfer | 01 lxi Data transfer
19 dad D Data transfer | 01 lxi Data transfer
1A ldax D Control | 00 nop Control
1B dcx D Data transfer | 01 lxi Data transfer
1C inr E Data transfer | 01 lxi Data transfer
1D dcr E Data transfer | 01 lxi Data transfer
1E mvi E Control | 00 nop Control
1F rar Data transfer | 01 lxi Data transfer
20 rim Control | 00 nop Control
21 lxi H Data transfer | 01 lxi Data transfer
22 shld Data transfer | 01 lxi Data transfer
23 inx J Control | 00 nop Control
24 inr H Data transfer | 01 lxi Data transfer
25 dcr H Data transfer | 01 lxi Data transfer
26 mvi H Control | 00 nop Control
27 daa Data transfer | 01 lxi Data transfer
29 dad H Data transfer | 01 lxi Data transfer
2A lhld Control | 00 nop Control
2B dcx H Data transfer | 01 lxi Data transfer
2C inr L Data transfer | 01 lxi Data transfer
2D dcr L Data transfer | 01 lxi Data transfer
2E mvi L Control | 00 nop Control
2F cma Data transfer | 01 lxi Data transfer
30 sim Data transfer | 01 lxi Data transfer
31 lxi SP Control | 00 nop Control
32 sta Control | 00 nop Control
aci
Opcode Operand Bytes M-Cycles T-States Hex code
ADI 8 bit data 2 2 7 C6
Description:- The 8-bit data and carry flag are added to the contents of the accumulator, and the result is stored in the
accumulator.
Flag:- All flags are modified to reflect the result of the addition.
Example:-
Initial state:- Regs/Mem Flags
A = 26H Cy=1
Instruction :- ACI 57H
Result :- Regs/Mem Flags
A = 7EH S=0, Z=0, Ac=0, P=1, Cy=0
Comments :-
1. After adition the previous carry flag is cleared.
2. This instruction is commonly used in 16-bit addition. This
instruction should not be used to account for a carry generated
by 8-bit numbers.
adc
Adc, Add register to accumulator with carry
Opcode Operand Bytes M-Cycles T-States Hex code
ADC Reg/ 1 1 4 Reg Hex
Mem 2 7 B 88
C 89
D 8A
E 8B
H 8C
L 8D
M 8E
A 8F
Description:- The contents of the operand (register or memory) and
and the Carry flag are added to the contents of the accumulator and
the result is placed in the accumulator. The contents of the operand
are not altered; however the previous carry flag is reset.
Flag:- All flags are modified to reflect the result of the addition.
Example:-
Initial state:- Regs/Mem Flags
A = 98H Cy=1
C = A1H
Instruction :- ADC C
Result :- Regs/Mem Flags
A = 3AH S=0, Z=0, Ac=0, P=1, Cy=0
Comments :-
1. After adition the previous carry flag is cleared.
2. This instruction is commonly used in 16-bit addition. This
instruction should not be used to account for a carry generated
by 8-bit numbers.